1. Field of the Invention
The present invention relates to a process for controlling a programmable controller or other control apparatus comprising special function units for performing control operations other than sequence control in accordance with commands from a CPU.
2. Description of the Prior Art
Programmable controllers were initially considered merely as a replacement for relays. However, the ease with which these controllers are programmed and their flexibility and functional capacity have expanded the programmable controller's field of application. Accordingly, programmable controllers are now employed not only for sequence (digital) control, but also analog control, position processing, communication processing, and monitoring displays. Sequence control is chiefly performed by a CPU module within the programmable controller. The other controller applications are mainly performed by special function modules. The CPU module also performs integrated control of the entire programmable controller by writing directive data and reading resultant data from the special function modules. Special function modules are essential for control of systems which continue to increase in scale and complexity.
Data transfer between the CPU module and special function modules will now be described.
FIG. 5 illustrates a system configuration diagram of a programmable controller known in the art, which includes a CPU module 1 for controlling the entire programmable controller, a program memory 11 for storing sequence programs, a device memory 12 for storing data employed in and resulting from the sequence programs, and a programming device 2 for writing the sequence programs to be stored in the program memory 11. This system also includes a communication cable 3 for connecting the CPU module 1 and the programming device 2, input/output modules 4, special function modules 4A and two-port memory 41 acting as a bidirectional access memory which allows data transfers between the special function modules 4A and CPU module 1.
FIGS. 6a to 6c provide structural examples of the two-port memory 41. FIG. 6a represents the two-port memory 41A of a two-channel digital-to-analog module. FIG. 6b illustrates a two-port memory 41B of an eight-channel D/A converter module, and FIG. 6c illustrates a two-port memory 41C of a display module.
FIG. 7 sets forth the format for instructions controlling data transfer between the CPU module 1 and the special function modules. The instruction 5 for reading data from the special function module 4A includes an I/O number 51 corresponding to the I/O position at which the special function module 4A is installed, and the head (i.e. first) address 52 of the two-port memory 41 from which data in the special function module 4A is to be read. The CPU instruction also includes a device head address 53 indicating the first address in the device (CPU) memory 12 to which the data is to be written, and the number of data points 54 to be transferred. The instruction 6 for writing data to a special function module includes an I/O number 61 corresponding to the I/O position at which the special function module 4A is installed, the head address 62 of the two-port memory 41 to which the special function module 4A data is to be written, the head device address 63 of the device (CPU) memory 12 from which the data is read, and the number of data points 64 to be transferred.
Examples of instructions for transferring data to the special function module 4A in the CPU module 1 are illustrated in FIG. 8. Instruction 6A writes one data point from the contents of device D0 to address 2 of the two-port memory 41 in the special function module 4A installed in I/O position 50. Instruction 6B writes one data point from the contents of device D0 to address 8 of the two-port memory 41 in the special function module 4A installed in I/O position 50.
However, the prior art includes a limited number of instruction types for the special function modules, such as FROM and TO instructions, which are employed to perform processing with respect to all special function modules. Thus, each instruction may have a different meaning depending upon which two-port memory receives the instruction. For instance, the program 6A sometimes operates as an analog output instruction to the first channel and sometimes as a display instruction, as will be explained below.
The user creates (FIG. 4A) the instructions shown in FIG. 8 with the programming device 2 and writes them to the program memory 11 of the CPU module 1 via the communication cable 3. When running the program step 6A, the CPU module 1 writes the contents of device DO in the device memory 12 to address 2 of the two-port memory 41A, 41B or 41C for the special function module installed in the I/O module at position 50 (which is specified in program 6A). Each special function module interprets this instruction in a different manner.
If a 2-channel D/A conversion module is installed at this I/O module position (the structure for which is set forth in FIG. 6a), the module outputs an analog value corresponding to the contents at address 2 of the two-port memory 41A.
However, if a display module is installed as the special function module 4A, then the instruction 6A represents a program for displaying a character corresponding to the contents of device DO at a display position stored in the buffer memory head address "2". In the example format (FIG. 6) for a display module, this address represents line 1 and column 3. Thus, the display module outputs a character corresponding to the contents at address 2 of the two-port memory 41C.
Program step 6B (FIG. 8) represents an instruction for outputting an analog value corresponding to the contents of device DO to a channel of an eight-channel digital-to-analog converter module (a special function module having eight digital-to-analog conversion facilities) installed in the I/O position 50. In this case, as indicated by the two-port memory structure in FIG. 6b, the contents of device D0 will be written to address 8 of the two-port memory 41B.
The user creates the instruction 6B from the programming device 2 and writes it to the program memory 11 of the CPU module 1 via the communication cable 3. Thereafter, the CPU module 1 writes the contents of device D0 in the device memory 12 to address 8 of the two-port memory 41B in the eight-channel digital-to-analog converter module (FIG. 6B) installed in the I/O position 50 specified in that program 6B. The eight-channel digital-to-analog converter module outputs an analog value corresponding to the contents at address 8 of the two-port memory 41B.
When an analog output is to be provided to the first channel of the digital-to-analog module, the program step will resemble 6A or 6B depending on the number of channels of the digital-to-analog module. Another program is employed if the digital-to-analog converter module includes 16 channels.
The prior art programmable controller controlling process, as described above, has few instruction types for the special function modules which are employed to perform all processing with respect to the special function modules. This has created the following problems: (1) that the same instruction is used to command entirely different operations, (2) that the format of an instruction cannot indicate which operation that instruction represents, since the instruction may differ in format with respect to the same operation, and (3) that when writing a program the addresses of the multi-directional access memory must be considered to ensure that the program step is sent to the correct special function module, which complicates programming.